1. Field of the Invention
The present invention relates to a booster circuit employing a switching element having a triple-well structure.
2. Description of the Related Art
In recent years, flash memories, which are a type of non-volatile semiconductor memory devices, require data read and data write using a single power supply voltage or low power supply voltages, for which, therefore, a booster circuit for supplying a positive or negative boosted voltage is required on a chip when each operation is performed. Also, during CMOS processes, a power supply voltage generated by the booster circuit is used to improve characteristics of an analog circuit.
Conventionally, there is a known booster circuit employing a triple-well structure switching element (U.S. Pat. Nos. 6,100,557, 6,121,821, and 7,102,422).
FIG. 25 shows an exemplary conventional booster circuit. In FIG. 25, 901 indicates a booster circuit which receives two-phase clock signals CLK1 and CLK2 and generates an output terminal voltage (boosted voltage) Vpump by a boosting operation. 902, 903, and 904 are boosting cells which constitute an exemplary three-stage configuration, where CLK1 is input to the odd-numbered-stage cells and CLK2 is input to the even-numbered-stage cell. 905 indicates a backflow preventing circuit which prevents backflow of the boosted voltage Vpump. 906 indicates a charge transfer transistor which functions as a switching element. 907 indicates a P well (PW) of the charge transfer transistor 906. 908 indicates a deep N well (NT) including the P well 907. 909 indicates a parasitic diode between the P well 907 and the N well 908. 910 indicates boosting capacitors which boost output terminals of the boosting cells 902, 903, and 904. 911, 912, 913, and 914 indicate I/O terminals of the boosting cells. As shown in FIG. 25, the P well 907 and the N well 908 of each charge transfer transistor 906 of the boosting cells 902 to 904 is connected to the source of the charge transfer transistor 906 so that they have the same potential.
FIG. 26 is a waveform diagram showing the two-phase clock signals CLK1 and CLK2 in the booster circuit 901 of FIG. 25. An operation of the booster circuit 901 of FIG. 25 will be briefly described with reference to FIG. 26.
Initially, at time T1, CLK1 goes to “H” (power supply voltage Vdd) and CLK2 goes to “L” (ground voltage Vss), so that the potentials of the I/O terminals 912 and 914 are boosted. At the same time, changes are transferred from the I/O terminal 912 to the I/O terminal 913 and from the I/O terminal 914 to the output terminal of the booster circuit 901, via the charge transfer transistors 906 of the boosting cell 903 and the backflow preventing circuit 905, respectively, so that the output terminal voltages of the I/O terminal 913 and the booster circuit 901 are increased. In this case, since the P well 907 of each of the boosting cell 903 and the backflow preventing circuit 905 has the same potential as that of the source terminal of the charge transfer transistor 906, the substrate biasing effect of the charge transfer transistor 906 is suppressed, thereby making it possible to suppress a decrease in charge transfer efficiency.
At time T2 when a charge transfer period Ttrans has been passed since time T1, CLK2 goes to “H” and CLK1 goes to “L”, so that the potential of the I/O terminal 913 is boosted. At the same time, charges are transferred from the I/O terminal 913 to the I/O terminal 914 via the charge transfer transistor 906 of the boosting cell 904. In this case, since the P well 907 of the boosting cell 904 has the same potential as that of the source terminal of the charge transfer transistor 906, the substrate biasing effect of the charge transfer transistor 906 is suppressed, thereby making it possible to suppress a decrease in charge transfer efficiency.
At time T3, an operation similar to that at time T1 is performed.
Thus, according to the booster circuit 901 of FIG. 25, the substrate biasing effect is suppressed, thereby making it possible to suppress a decrease in charge transfer efficiency during the boosting operation.
However, in the conventional booster circuit 901, the source and the N well 908 of the charge transfer transistor 906 are connected to each other, so that a parasitic capacitance formed by the N well 908 is charged and discharged by voltage transition widths of the clock signals CLK1 and CLK2 in response to voltage transitions of the clock signals CLK1 and CLK2.
Also, charges supplied by the clock signals CLK1 and CLK2 are used to charge and discharge the N well 908, disadvantageously resulting in a decrease in boost efficiency.
Also, since the source and the N well 908 of the charge transfer transistor 906 are connected to each other, it is necessary to separate the N wells 908 of the charge transfer transistors 906 from each other, disadvantageously resulting in an increase in layout area.